1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device such as a mask read-only memory (ROM).
2. Description of the Related Art
A mask ROM is composed of a memory portion and its peripheral portion, Also, in the peripheral portion, isolation between elements is carried out by a thick field insulating layer obtained by a so-called local oxidation of silicon (LOCOS), while in the memory portion, isolation between elements is carried out by a groove (trench) configuration (see: T. Nishizaka et al: "32 Mbit Very High Density Mask ROM", NEC Res. & Develop., Vol 32, No. 1, January 1991, pp 48-51).
In a prior art method for manufacturing a memory portion of mask ROM, a conductive layer made of polycrystalline silicon, for example, is formed on a semiconductor substrate. Then, the conductive layer is etched, and a groove is formed within the semiconductor substrate where the conductive layer is removed. Then, an isolation insulating layer made of boron phosphorus silicate glass (BPSG) is buried within the groove, which will be explained later in more detail.
In the above-mentioned prior art method, however, a side face of the conductive layer is perpendicular or forward-tapered. If the side face of the conductive layer is perpendicular, voids may be easily generated within the buried isolation insulating layer, thus deteriorating the reliability of the mask ROM. On the one hand, if the side face of the conductive layer is forward-tapered, voids may be hardly generated within the buried isolation insulating layer. In this case, however, even when anisotropic etching is performed upon the conductive layer, such etching is incomplete, i.e., the portion of the forward-tapered conductive layer remains, thus inviting a short-circuit.